1. Field of Invention
The present invention relates to a digital to analog converter, and more particularly to a digital to analog converter with resistance network with a resistance compensatory circuitry which is adapted to optimally convert a digital signal into an analog signal for use by analog-type LCDs.
2. Description of Related Arts
Liquid Crystal Displays (LCD) have been widely accepted as a major alternative to traditional Cathode-Ray Tube (CRT) display. They have the advantages of being smaller in size, clearer in displaying images, and substantially reducing radiation. There exist two major types of LCD, namely, analog and digital LCDs. The distinction implies that the LCD in question may only accept respectively, analog or digital signals for displaying a particular image on the screen. In order to process digital signals in an analog LCD, or vice versa, it definitely requires a converter which is capable of converting a digital signal into an analog signal or vice versa.
Generally speaking, analog LCDs enjoy considerable competitive power as compared with digital LCDs. What this implies is that the need for a better quality converter never stops. As a matter of fact, almost all converters which are capable of transforming digital input signals into analog output signals involve certain loss or distortions in the signal converted. The key question becomes how to minimize such loss or distortion during signal conversion, while at the same time keeping the conversion process efficient and economical.
A digital to analog converter with improved switched R-2R network is described in U.S. Pat. No. 6,222,473. There are a variety of digital to analog converters available for converting digital input signals into analog output signals depending upon the desired conversion functionality. The variations in the digital to analog converters available may have different predetermined resolutions of a digital input signal, receive different encoded digital input signals, have different ranges of analog output signals using a fixed reference or a multiplied reference, and provide different types of analog output signals. Additionally, there are a number of digital to analog converter performance factors to consider such as settling time, full scale transition time, accuracy or linearity, and a factor previously mentioned, resolution.
The digital input signal is a number of bits wide, defining the resolution, the number of output levels or quantization levels and the total number of digital codes that are acceptable. If the digital input signal is n-bits wide, there are 2n output levels and 2 n−1 steps between levels. The digital input signals may be encoded in straight binary, two's complement, offset binary, gray scale code, binary coded decimal or other digital coding. The range of analog output signal values usually depends upon an analog reference. The analog reference may be internally generated but is usually externally provided for precision. The analog output signal range may be proportional to the digital input signal over a fixed analog reference level as in a fixed reference digital to analog converter. Alternatively, the analog output signal may be the product of a varying input analog reference level and the digital code of the digital input signal as in multiplying digital to analog converters. The analog output signal may be unipolar ranging in either positive values or negative values or it may be bipolar ranging between both positive and negative output values. The analog output signal may be an analog voltage signal or an analog current signal.
Additionally, the type of electronic circuitry used to form a digital to analog converter varies as well. Bipolar junction transistor (BJT) technology, metal oxide semiconductor (MOS) technology or a combination thereof is used to construct digital to analog converters. BJT technology may be PNP technology with PNP transistors or NPN with NPN transistors or both, while MOS technology may be PMOS with P-channel field effect transistors (PFET), NMOS with N-channel field effect transistors (NFET) or CMOS technology having both PFETs and NFETs.
Referring to FIG. 1 of the drawings, a conventional digital to analog converter is usually embodied as an R-2R network digital to analog converter comprising a R-2R network. The R-2R network digital to analog converter usually comprises an R-2R network 121, a switching circuitry 111, and a digital signal input 131 which contains a four digital input terminals D0, D1, D2, D3, appeared in the FIG. 1.
The R-2R network 121 comprises resistors 124, 126, 128 each having a predetermined resistance r, resistors 122, 123, 125, 127, 129 each having a predetermined resistance R which is twice the resistance r. In other words, R=2r.
The switching circuitry 111 comprises four switches 112, 113, 114, 115 wherein each of the switches 112, 113, 114, 115 comprises an inverter 201, a CMOS transmission gate 202, two PMOS transistors 212, 222, and two NMOS transistors 213, 223.
The R-2R network digital to analog converter usually comprises the digital input 131, the R-2R network 121, the switching circuitry 111, and the digital input 131, an analog supply voltage level VDD, and a ground level GND. The digital input terminals D0, D1, D2, D3 individually control switches 112, 113, 114, 115 to cause the R-2R network digital to analog converter convert the value of the digital input 131 into the analog output signal. The linearity of an R-2R network digital to analog converter is very important for accurate conversions and is usually specified in units of least significant bits (LSB) of the n-bit of the digital input 131. Under an idealized situation the R-2R network digital to analog converter could have a good linearity for accurate conversions if the resistance of each resistor of the R-2R network 121 is greater than the intrinsic resistance of the corresponding switches 112, 113, 114, 115.
There are disadvantages regarding this conventional R-2R network digital to analog converter which is applied to an analog LCD. A conventional analog LCD comprises a RGB terminal comprising a red video terminal, a green video terminal, and a blue video terminal for receiving analog RGB signals respectively through a convention AV cable comprising three wires, which are connected to the analog LCD via the video red terminal, the video green terminal, and the video blue terminal respectively. The equivalent input impedance of each of the video red terminal, the video green terminal, and the video blue terminal of the analog LCD could be treated as a capacitive loading. As a result, when the conventional R-2R network digital to analog converter is utilized in practice, one may implement three separate R-2R network digital to analog converter for converting three distinct digital signals, video red signal, video green signal, and video blue signal, to three distinct analog signals. The resistances of resistors 124, 126, and 128 of the R-2R network 121 and resistors having a predetermined resistance 2r must be reduced in order to change the analog output voltage from a maximum value to a minimum value or vice versa in a fixed unit time period when the input signals of the digital input terminals D0, D1, D2, D3 of the digital input 131 are suddenly changed from high voltage levels to low voltage levels or vice versa. However, the linearity of the R-2R network digital to analog converter becomes poor when the resistances of resistors of the R-2R network 121 are reduced. In other words, signal distortion or loss is expected to be very severe. It is due to that the resistance of each resistor of the R-2R network 121 is not greater than the intrinsic resistance of the corresponding switches 112, 113, 114, 115.
Referring to FIG. 3 of the drawings, in order to resolve these severe distortion and signal loss problems, a unity gain buffer 321 is coupled to the R-2R network digital to analog converter 301. With the help of the unity gain buffer 321, the resistances of the R-2R network digital to analog converter 301 would select an optimal value which is greater than intrinsic resistance of the switches 303,304,305,306 in order to optimize the performance of the digital-analog converter.
However, a major drawback of employing this unity gain buffer 321 is that a high quality unity gain buffer 321 is usually expensive. Moreover, the performance of the digital to analog converter is then solely dependent on the performance and characteristics of the unity gain buffer 321 such that the flexibility in introducing any additional features to the R-2R network digital to analog converter is substantially undermined.